This invention relates, in general, to memory cell sensing, and more particularly to increasing the speed at which the memory cell logic state can be transferred to the output of a static random access memory (SRAM).
Semiconductor manufacturers are continually increasing the number of memory cells which can be built into an SRAM. The increase in memory density is due mainly to shrinking semiconductor device sizes through advances in semiconductor process technology. Users of SRAMs want memory densities and memory performance to increase simultaneously. From a design perspective, adding memory cells to an SRAM will decrease memory performance by adding parasitic capacitance to the memory array and slowing circuits which drive the larger capacitive load.
Large memory array sizes have a severe impact on memory cell sensing. Reducing the size of a memory cell, is mainly accomplished with smaller transistor sizes in the memory cell. Although the smaller memory cell will have a smaller parasitic capacitance, the increased number of memory cells and the reduced drive strength of the smaller transistors (in the memory cell) have a net effect of slowing memory cell sensing.
To counter the increased capacitance of larger memory arrays, block architected SRAMs are built to break the large memory array into smaller arrays which can be individually or simultaneously accessed. The tradeoff of building a block architected SRAM is the addition of block decode circuitry and the extra silicon area needed to implement the additional decode scheme. Almost all high density SRAMs use a block architecture to enhance memory performance.
A memory block comprises a number of memory cell rows and columns. An individual memory cell logic state is sensed from a memory cell column. The memory cell to be sensed is the only cell activated in the memory cell column. Each memory cell column has a first bit line and a second bit line to which all memory cells in the column are coupled. The first bit and second bit lines are charged to a predetermined voltage. The enabled memory cell creates a differential voltage across the first bit line and second bit line signifying the memory cell logic state.
A sense amplifier is coupled to the first bit line and the second bit line. The sense amplifier amplifies the differential voltage created by the memory cell. The amplified differential signal is coupled to an output level translator circuit. The output level translator converts the differential signal into a binary logic state corresponding to the memory cell logic state. The output level translator may couple to a buffer or tri-state buffer to drive a capacitive load.
As memory arrays continue to increase in size, it will be important to provide new techniques which improve performance in memory cell sensing, thereby allowing higher density SRAMs to also operate at faster speeds.